The style is just simply coming onto the marketplace and info is actually not possible to reach by. And so this’s the first of countless articles, so you have to go no further. Exactly who has not wanted to get those couple of additional MHz performances out of their FPGA? Here is just how I do it. I am going to describe what it takes to develop a layout which meets timing constraints using style techniques. The contents of this report are definitely the opinion of mine. Please feel free to provide me suggestions.
To cut to the chase, let us go over a number of layout guidelines of what you need to and should not do. Several of these’re intentionally basic, but in order to get the performance you have to take a look at every element of the design of yours. Prior to the design process, make sure that you buy now your FPGA from reliable sources to ensure great performance.
What you should do and what to avoid. First a summary of dos. Do correctly specify your FPGA layout – make certain you understand what you, and even more important you colleagues and buyer want, particularly with design. Do use as little some clocks as you can and synchronize FPGA resets to the right clocks. Simulate the entire FPGA design; block amount is not sufficient and if possible the whole board or perhaps system. Do synchronize transfers across clock domains. Make utilization of the embedded FPGA specific characteristics, e.g., SRLs.
Constantly do an FPGA test look with the pinout before committing to board layout! Confirm that there aren’t any banking or perhaps clocking limitations. It does not matter what the FPGA examination design does make certain that not one of the logic is actually optimized away. Do have some extra FPGA with external pull ups. These may be hooked up to for modifying output and input. Do use high speed serial I/O rather compared to higher pace parallel input and paper. As a rule of thumb, permit five % in addition to you demanded clock speed to account for temperature, clock jitter as well as racket fluctuations within the FPGA.
Today a summary of does not do’s. Do not make use of some more clocks than is needed and stay away from asynchronous logic latches. Do not over constrain the design of yours. Do not write woolly HDL if you would like top overall performance from the FPGA, spell it out to the synthesis application so trinomial logic is converted by it to fast logic. Do not make assumptions; understand what the consequences of your code are actually. Do not count on IP blocks to out perform the computer of yours, just since it is made by a so called trinomial specialist does not mean you cannot do some thing better or perhaps more effectively, or perhaps more particular to the goals of yours.